Crosstalk is a register-transfer level design sandbox with a built-in simulator and emulator. Players build designs ranging from LED controllers to entire computers using SystemVerilog. It has a gate-level simulator, a terminal emulator, an oscilloscope, introspection tools, a compiler, and more.

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Coming Soon To Early Access

The developers of this game intend to release as a work in progress, developing with the feedback of players.

Note: Games in Early Access are not complete and may or may not change further. If you are not excited to play this game in its current state, then you should wait to see if the game progresses further in development. Learn more

What the developers have to say:

Why Early Access?

“We would like to iterate on the game on a frequent basis as we go instead of relying on standard patch cadence that would come with a 1.0 release. The input of players will help determine what is wanted and what isn't.”

Approximately how long will this game be in Early Access?

“As far as we can tell at the moment of writing, the Early Access stage will last well through 2027 and likely conclude within 2028 (earlier rather than later in the year).”

How is the full version planned to differ from the Early Access version?

“We have a lot planned for Crosstalk. We recognized the potential of it during our planned 1.0 release, which we had to postpone, noticing that given the game's current theme, a lot could be built on top of it. Concretely, a few of the features that we want to work on include a full reverse-engineering suite that will go hand-in-hand with the RTL and emulation suite. Separately, once done with that, we want to add PCB authoring and editing, custom integrated circuit design, PCB scanning and importing, and external component import using just datasheets.

Additionally, the originally announced city-builder mode is set to be released at 1.0 instead of at the launch of Early Access. While building the player interaction surface and the presentation layer of it, something felt off, and we don't want to push it without identifying the cause. We also have a very specific visual direction when it comes to that mode, which we haven't been able to realize yet. The logic is there, but what the player sees while playing it is not what we want to release so early. As such, the feature is scheduled for the 1.0 release.

The EDA features, including the PCB editor, are estimated to release during Early Access.”

What is the current state of the Early Access version?

“Crosstalk currently focuses on RTL design. It comes with a SystemVerilog parser, elaborator, C emitter, synthesizer, simulator, and an emulator. There is also a compiler included. Designs that have already been described in SV can be programmed and interfaced with using a built-in terminal emulator with a serial interface, which players can connect to real-world external hardware, such as microcontroller boards, instruments, sensors, and so on. There are display output simulators that offer a period-specific theme to display output, if desired. A player could pick from CRT, gas-plasma, and modern LCD. Sound emission is also supported, which lets certain ICs act as sources, whether ones reading existing audio or synthesizing sound on the fly.

The game is heavily integrated with social features (Steam Chat, leaderboards, Steam Stats, Discord Social SDK, pair-play focused statistics) and has 78 achievements configured at the time of writing.

Crosstalk integrates with the Steam Workshop and lets players share their designs as a whole, but also their individual processor architectures and cores, and software for their architectures.

The PCB-related features previously announced are not in the Early Access build anymore and are instead scheduled for a later release during Early Access. A Community post about this includes more details.”

Will the game be priced differently during and after Early Access?

“With releases containing brand new features during Early Access, we do plan to increase the price. At 1.0 and subsequent major version bumps, we plan to increase the price as well. We also plan to engage with seasonal discount events and Fests, where applicable, which will reduce the price for the duration of such events.”

How are you planning on involving the Community in your development process?

“We will interface with players via the Community Hub and the Discord server that we started for the game. People will be able to discuss ideas, new features, issues, and fan content (esp. the Workshop).”
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This game is not yet available on Steam

Planned Release Date: Sep 9, 2026

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About This Game

The mission statement of Crosstalk is that we would like it to bring back the joy of tinkering, designing things from near-scratch, and taking one's time with something, all while letting people connect and collaborate. We don't see that much anymore in computing.

Crosstalk, noun, engineering

"Crosstalk between signal channels denotes the interactive influence between two independent channels as a result of leakage currents and capacitive or inductive coupling. Crosstalk between the channels changes the signal by the value of the amplitude of the crosstalk signal."

- Siemens: SIMATIC ET 200AL Manual Collection

Crosstalk is an RTL sandbox with a simulator and an emulator for building electronics. Players can construct and program devices ranging from calculators to complex computers. It comes with a gate-level SystemVerilog simulator that consists of an elaborator, a synthesizer, and a C emitter, plus the Clang compiler, which compiles the emitted C code and runs it for faster design execution. The C code is derived from players' own SystemVerilog.

The default workflow is opening the RTL workspace, entering a shell, describing a design in SystemVerilog, programming it, and then writing software for it. The game supports a networked mode, in which one collaborates with other players.

Designs (cores, software, emulators) can all be shared via the Workshop.

Serial interface

Crosstalk can interface with devices using virtual in-game serial ports or the running machine's physical serial interface, which is /dev/ttyUSB<n> and /dev/ttyACM<n> on Unix and COM<n> on Windows, or its own shell interface. External devices can thus be plugged directly into designs and be represented by stand-in parts. Players could use microcontrollers, sensors, physical buttons, or even other computers.

The supplied truecolor terminal emulator can be used as a serial terminal I/O device. It is ANSI/VT100/xterm/kitty-compatible and can interact with the host over a PTY/ConPTY

Serial I/O works with physical devices. The above is TX.

RX

Scopes

Memory view of the running design and an oscilloscope are necessary tools while building, so they're both included and easily accessible to players.

Memory view and runtime activity indication

An oscilloscope attached to a signal, like sound output

Display output

If a design has a video display output, then players can use one of the three built-in display modes: CRT, gas-plasma, and modern LCD. The concrete interfaces used are CGA (for CRT and gas-plasma) and VGA.

A CGA gas-plasma display output type showing the DANGLING kernel booting on an i386-compatible CPU, in-game

The in-game displays are interactive

CPU architecture design

Players can define ISAs and then view a help banner in the game while developing. Later on, a DLC with a guided ISA design feature set will be released.

The Minimal Instruction Set Computer ISA

Runtime register state overview

A stack view that shows a trace on faults

Program locator overview

The program-level Profiler mode shows where time is going during a program's runtime

SystemVerilog

FPGA designs can be described using vendor-neutral SystemVerilog. The designs can be RTL-simulated. For accelerated simulation, there is a built-in option to emit C99 from the supplied SystemVerilog using Crosstalk's toolchain and the enclosed Clang compiler, or run it in emulation mode, which disables design accuracy guarantees and reproduces the design behaviorally instead, using the built-in emulator. For high-resolution simulation, a gate-level simulator is available, which runs a synthesized variant of the design. This is an expensive operation, so it takes much longer and is capped to smaller designs.

The included Profiler shows an overview of where cycles within the SV design are spent

The interactive Schematic viewer shows both the RTL and the gate-level schematic and in profile mode, highlights hot cells

Sandbox mode

Self-play submode

Sandbox mode is the default Crosstalk experience. Players can create a custom workspace with resizable, positionable, and alignable floating windows. Most use-cases start with opening a shell session to their host, invoking their editor, and writing SystemVerilog. Once there is a valid design, it can be simulated inside Crosstalk.

Networked submode

In this submode, one can team up with others over Steam Networking and build together. It is structurally identical to Self-play mode, but with networking enabled.

System Requirements

    Minimum:
    • Requires a 64-bit processor and operating system
    • OS: Windows 10 1809
    • Processor: 2.4GHz quad-core
    • Memory: 4 GB RAM
    • Graphics: VRAM >=4Gi
    • Network: Broadband Internet connection
    • Storage: 3 GB available space
    • Additional Notes: Vulkan >=1.3 required; simulated clock linearly follows single-core frequency multiplied by IPC
    Recommended:
    • Requires a 64-bit processor and operating system
    • OS: Windows 11
    • Processor: 4.6GHz octa-core
    • Memory: 16 GB RAM
    • Graphics: VRAM >=12Gi
    • Network: Broadband Internet connection
    • Storage: 10 GB available space
    • Additional Notes: Vulkan >=1.3 required (discrete Vk device recommended); simulated clock linearly follows single-core frequency multiplied by IPC
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